Keywords: synthesis tools, hardware/software codesign, partitioning, verification, specification, CAD, VLSI design
Start Date: 1 October 94 / Duration: 36 months
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This project comes in collaboration with COBRA, the ESPRIT project on COdesign Basic ReseArch, whose aim is to develop partitioning techniques for hardware-software codesign based on existing specification methods, and to integrate them with design-verification and high-level synthesis tools. The goals are to enhance existing partitioning techniques by introducing hierarchy and abstraction concepts in the partitioning algorithm, as well as to define and implement a generic model for the target architecture which will be taken into account in the partitioning method. The first goal has been achieved using timed Petri nets as an intermediate format for the partitioning algorithm. The second aim is the development of an environment to specify and generate template architectures. The approach is based on Petri net specifications.
The original version of the partitioning algorithm was ported for use with C language and a version for specifications in Occam was implemented. The use of timed Petri nets as an intermediate format for the hardware-software partitioning algorithm was analysed and an Occam/Petri net translator was developed. Time analysis methods are now being studied. Different memory organisation models and communication mechanisms have been analysed, as well as distinct topologies for interconnecting networks. A library of communication protocols, interconnection topologies, and microprocessors is being developed. Additional activities include a front-end VHDL tool for the high level synthesis system CADDY, to permit the high-level synthesis of VHDL descriptions. A further related activity is the formal verification of the partitioning process. This research work was a task in the ESPRIT COBRA project, and is also a work package in the ongoing PISH, a project at Tubingen University. One of the goals is to guarantee that partitioning preserves the semantics of the original description. This is achieved by transforming the original description into a program whose structure reflects the hardware and software components and how they interact, to achieve the overall goal. This work is related to another KIT activity, KIT 142.
The partitioning approach was presented in April 96 at a seminar in Germany. Papers concerning the intermediate format were presented in the Workshop on Rapid Prototyping held in Greece in May 1996, in the First Brazilian Workshop on Hardware-Software Codesign, and in the IX Brazilian Symposium on Integrated Circuit Design which took place in March 1996. A case study in the area of biomedical instrumentation has started in a cooperation with the University of Pernambuco.
University of Tübingen
University of Tübingen, D
Electronic Laboratory VTT, Oulu, SF
Univ. Politecnica de Madrid, E
University of Denmark, Lyngby, DK
University of Pernambuco, BRZ
Prof. Dr. W. Rosenstiel
Tel: +49 7071 297 54 82
Fax: +49 7071 610 399
CODESIGN - KIT128, May 1997
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook