A Unified Built-In Self Test Approach for Full Defect Testing in Mixed Signal (Analogue-Digital-Mixed) Devices


UBISTA - CP94-391

Keywords: built-in self-test (BIST), defect testing, signal processing, mixed mode devices, reliability


Start Date: 1 March 95 / Duration: 36 months

[ participants / contact]


Objectivies and Approach

The objective of this research is the development of a complete, defect oriented test strategy for self testing mixed signal devices and a design support system for the design and development of self testing mixed signal devices. The system will consist of a test pattern generation and evaluation unit, a dedicated fault effect monitor and the necessary analogue and digital functional units. The basis of the approach is current monitoring, a testing technique which can be used for both analogue and digital designs. All results will be evaluated on practical designs.

The ongoing research focuses on: the development of suitable built-in current monitors for the measuring and evaluation of both quiescent and dynamic currents; the optimisation and integration of the OCIMU off-chip current monitor and the development of an easy to use, general purpose current monitor; the evaluation of current test based strategies for testing different classes of analogue circuits, with special attention for current mode circuits; the evaluation and improvement of common analogue building blocks in function of defect oriented test strategies, and the development of suitable design guidelines for the development of such building blocks; the establishment of the link between the optimal test pattern set and the optimal TPG (Test Pattern Generation) automata to generate the test pattern set and to compress the test results, together with the necessary software to evaluate the effectiveness of the test carried out.

European links: ESPRIT Basic Research Action ATSEC (6575), TEMPUS project JEP-1565, project DARTS (CP92-7399), project FUTEG (CP93-9624).

Progress and Results

The results obtained so far are: design and realisation of a current conveyor based BIC monitor for low voltage (3.3V) ASICs; the improvement of the OCIMU off-chip monitor; the development of a current based BIST strategy for current mode circuits, together with the design and realisation of a suitable demonstrator, i.e. a notch filter, part of a telecom data path.

Information Dissemination Activities and/or Exploitation

The results will be disseminated through published papers and presentations at conferences, as well as workshops for industry. The improved OCIMU monitor is currently under evaluation by ALCATEL-Bell and ALCATEL-Mietec.


Coordinator

Katholieke Hogeschool Brugge-Oostende (KHBO)
Dep. Industrieele Wettenschappen en Technologie (IW&T)
Zeedijk 101
B-8400 Oostende, B

EU Partners

Katholieke Hogeschool Brugge-Oostende, B
Leeds Metropolitan University, UK

Non-EU Partners

Institute of Computer Systems of the Slovak Academy of Sciences, SK
Dept. of Microelectronics, Slovak Technical University of Bratislava, SK
Faculty of Electrical Engineering, Technical University of Brno, CZ
Central European Design Office (CEDO-Brno), CZ

CONTACT POINT

Ing. H. Manhaeve
Tel: +32 59 50 89 96
Fax: +32 59 70 42 15
E-mail: manhaeve@kh.khbo.be


INCO synopses home page INCO cooperation index INCO keyword index
INCO acronym index INCO number index INCO Projects index
All
synopses home page all keywords index all acronyms index all numbers index

UBISTA - CP94-391, May 1997


please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook