Synthesis of Image and Speech Processing Algorithms on Silicon

SISPAS - CP94-223

Keywords: speech processing, image processing, compression algorithms

Start Date: 1 September 95 / Duration: 36 months

Objectivies and Approach

The project concerns research and development activities focused on synthesis of image and speech processing algorithms on silicon. The technical activites will be:

algorithm design and evaluation of appropriate hardware architectures for VLSI implementation of image compression algorithms,
derivation of detailed architectures for VLSI implementation, emphasising high speed and low power optimisations for image and speech processing,
design and test of ASICs for two industrial applications with the aid of the Cathedral software; the work aims at providing key components for commercial digital signal processing (DSP) products, so all aspects of ASICS design and testing have to be addressed.

European links: CATHEDRAL was developed in ESPRIT Project 2260 (SPRITE).

Progress and Results

An algorithmic study has been initiated for different functions in a region oriented image compression scheme. High-level descriptions have been worked out for these blocks.

An architecture study has been performed for a generic digital modulator architecture. The different subfunctions are identified and the required parameters for each of them are derived. The set of the parametrised blocks form a library which can be used to produce dedicated modulator chips for applications. This customisation is done via the setting of the parameter values for each modulator factor.

Information Dissemination Activities and/or Exploitation

The CEDO will act as a service centre for prototype development and training for industry to implement new data compression algorithms with newly developed and/or commercial software tools. Workshops will be held in the countries of the East European partners, and industrial companies in these countries will be visited to explain the SISPAS opportunities available in the CEDO, to look for practical designs and to organise for them a training period with real life designs in the CEDO.

Coordinator

Interuniversity Microelectronics Center (IMEC)
Kapeldreef 75
B-3001 Leuven, B

EU Partners

Interuniversity Microelectronics Centre (IMEC), B
Katholieke Industriële Hogeschool W.-Vlaanderen (KIHWV), B
Vrije Universiteit Brussel (VUB), Brussel, B

Non-EU Partners

Czech Technical University (CTU), Prague, CZ
Slovak Technical University (STU), Bratislava, SK
Technical University of Brno (TUB), Brno, CZ
Central European Design Office (CEDO), Brno, CZ

CONTACT POINT

Ir. Serge Veralde
Tel: +32 16 281567
Fax: +32 16 281515
E-mail: vernalde@imec.be

SISPAS - CP94-223, May 1997

please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook