Keywords: functional test generation, VHDL test generation, partial boundary scan, module testing
Start Date: 1 March 1994 / Status: finished / Duration: 36 months
[ participants / contact]
The objective of this project is to develop a methodology for functional test generation in microelectronics. Testing and diagnosis have great problems in managing the complexity of a system design. One promising way to overcome these problems would involve functional aspects at the system level rather than structural ones at the gate level only. Then it will become possible for system level VHDL descriptions to be the basis for the generation of tests for validation and fault diagnosis.
Three different approaches will be pursued:
European links: ESPRIT Project ATSEC (6575), EEMCN (CP93-7668), ESPRIT Project EUROPRACTICE (21101), TEMPUS JEP 4772, UBISTA (CP94-0391), BENEFIT (CP94-536), HCM Network BELSIGN.
Investigations are carried out into developing a methodology for automating the test scheduling process, application of artificial intelligence to functional test generation, as well as a test methodology for partial boundary scan and its application to MultiChip module testing.
Results have been presented in two exhibitions in Jurmala, Latvia, and in Tallinn, 1996. To date, 34 technical reports have been elaborated by the partners. More information can be found at WWW, http://www.mmt.bme.hu/~pataric/futeg.html.
Fraunhofer Institut für Integrierte Schaltungen
D-01069 Dresden, D
Fraunhofer Institut für Integrierte Schaltungen IIS/EAS,
INPG/TIMA, Grenoble, F
Tallinn Technical University, EE
Kaunas University of Technology, LT
Institute of Computer Systems, Bratislava, SK
Technical University of Budapest, HU
Mr. Bernd Straube
Tel: +49 351 464 07 40
Fax: +49 351 464 07 03
FUTEG - CP93-9624, May 1997
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook