Design Automation for Real Time Signal Processing

DARTS - CP92-7399

Keywords: real time signal processing, silicon compilers

Start Date: 1 January 1994 / Status: finished / Duration: 24 months

[ participants / contact]

Objectivies and Approach

The objective of this project is to assess, optimise and transfer new design methodologies for complex, high performance digital signal processing (DSP) algorithms on ASICs to the industrial and academic community of the Czech and Slovak Republics. This will be achieved by creating centres of expertise in the Czech and Slovak Republics to perform research on new design methodologies for the realisation of systems on ASICs, by training designers of the Czech and Slovak systems industry in the development and extension of high level synthesis for DSP and by starting or rehabilitating collaboration between technical universities and industry in the Czech and Slovak Republics.

The project tackles also problems that are identified by designers using the Cathedral synthesis environment, with emphasis on extensions towards the realisation of high performance systems.

European links: The work transfers the Cathedral synthesis software developed in ESPRIT project 2260 (SPRITE).

Progress and Results

A complete, transferable design path from high level system specification to foundry has been installed at the universities and in-depth training, support and engineering activities have taken place. In order to produce a chip whose area is comparable with the one produced by human experts, a hardware address generation tool for high speed memory access and a tool to optimise the interconnect in the processor network have been developed. Furthermore, a formal verification methodology has been elaborated for the Cathedral silicon compiler. Moreover, an automated path has been developed from a high-level behavioural DSP algorithm, thus allowing the local industry to make low cost implementations for their DSP algorithms.

Information Dissemination Activities and/or Exploitation

A centre of competence, CEDO, has been established, which has demonstrated the applicability of the research results on relevant design problems of the industrial partners and is also involved in training and research projects. The collaboration so far gives the opportunity to improve the situation in electronic industries and universities in Czech and Slovak Republic. Thanks to work performed in the DARTS project, the Cathedral silicon compiler now provides a complete design path from high level specification to the foundry for industrially accepted hardware libraries.


Kapeldreef 75
3001 Leuven, B

EU Partners

Katholieke Industriële Hogeschool West-Vlaanderen, B
European Design Office, B

Non-EU Partners

Slovak Technical University, SK
Czech Technical University, CZ
Technical University of Brno, CZ
Tesla Piestany, SK
Tesla-Telekomunikace, CZ
ASI Centrum Tesla Vust, CZ


Ir. Serge Vernalde
Tel: +32 16 281567
Fax: +32 16 281515

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DARTS - CP92-7399, May 1997

please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook