Code Generation for Heterogeneous Information Processing Systems


CHIPS - 9138

Work Area: Basic Aspects of Multiple Computing Agents

Keywords neural networks, natural and artificial visual systems, architectural specifications


Start Date: to be announced / Status: starting

[ participants / contact ]


Abstract The goal of the project is to investigate methods and to implement tools for mapping algorithms of different nature to predifined hardware structures. Hardware structures in general will be allowed to be heterogeneous in the sense that they consist of processor cores, customised data path and memories. The target application domain is real-time information processing systems, to be implemented in VLSI chips.


Aims

The goal of the project is to investigate methods and to implement tools for mapping algorithms of different nature to predifined hardware structures. Hardware structures in general will be allowed to be heterogeneous in the sense that they consist of processor cores, customised data path and memories. The target application domain is real-time information processing systems, to be implemented in VLSI chips.

The heterogeneous nature of these systems, both in terms of functionality and implementation style, requires the support of mixed data and control processing functions to be mapped on those heterogeneous structures and the ability to easily change the structure of the target processor in order to explore different implementation alternatives. Tools supporting this degree of flexibility are called retargetable compilers.

Approach and Methods

Real-time data processing functions operate on sampled data streams, which must be processed at the required sample frequency or throughput, determined by the system's environment. On the contrary, control processing functions operate on variables which are processed at irregular, usually unconstrained, moments in time. The data and control processing functions mays be viewed as concurrent processes. When mixing these two paradigms together, a consistent model must be developed to describe their interaction. A synchronisation method must be developed for solving conflicts in the timing behaviour and in the access of the target processor. Retargetability will be accomplished by developing methodologies for matching patterns representing algorithms, and programmable hardware structures described by means of an HDL in terms of their structures and instruction sets. The result of the matching process will be the binary control for the targer programmable structure.

Potential

This project aims to reduce the effort required for implementing complex real-time information processing systems by a significant factor. The project will generate tools which are indispensable for analysing tradeoffs during hardware/software codesign, especially if programmable components for which commercial compiler support is poor, are used. Moreover, the ability to map control processing functions on the DSP core will allow to add new features to the information processing system, which may significantly increase the added value of the product. This functionality is extremely important for the personal communcation systems market, in which Europe is playing a dominant role (eg GSM cellular radio, DECT cordless phone). The technology that will be developed in this project aims at meeting stringent market requirements in the development of such systems.


Coordinator

Universität Dortmund - D
Informatik XII
Otto-Hahn-Strasse, 16
D- 44227 DORTMUND

Partners

IMEC - B
Università di Genova - Dist - I

CONTACT POINT

Peter Marwedel
tel +49/231 7556111
fax +49/231 755 6555
e-mail: marwedel@ls12.informatik.uni-dortmund.de


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CHIPS - 9138, August 1994


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html version of synopsis by Nick Cook