Copper Interconnection


COIN - 9021

Keywords multilevel metallisation, copper metallisation, electromigration performances


Start Date: 01-FEB-94 / Duration: 24 months

[ contact / participants ]


Objectives and Approach

The aim of COIN is to develop and to evaluate the basic process steps allowing the introduction of copper metallisation as a working solution for on-chip interconnections. Copper has attracted more and more attention as a new metallisation material because of its low electrical resistivity and much higher resistance to electromigration failure. Copper electromigration performances are superior by at least three orders of magnitude to the best values obtained for Al alloys. Products incorporating smart-power or bipolar technologies, which require very high current densities, could benefit immediately from copper metallisation.

The purpose is to limit the modifications of existing multilayer metallisation structures to a simple substitution of all the Al-based metallisation by copper.

The project will concentrate on the demonstration of the effectiveness against copper diffusion of the dielectric and barrier materials currently used in the interconnect structure. This will lead to the stabilisation and optimisation of barrier performances for these conductive (Ti/TiN, W) and dielectric (SiO[2]) materials. Electrical evaluation on active test structures will be performed before and after aging under thermal and electrical stresses to check the barrier layer efficiency against Cu diffusion towards the active parts of silicon devices. In parallel, work will be done on the development of basic process steps for copper deposition and patterning.

The main part of the activity concerning metal deposition will be focused on Cu-CVD, with a view to demonstrating the feasibility of the process and its evaluation versus specifications important for equipment and circuit manufacturers.

Concerning metal patterning, an accurate evaluation of the ion milling solution will be made using deep sub-micron dimensions. In parallel, RIE processes will be evaluated using existing equipment, modified to allow sample heating. The equipment modifications will be performed in collaboration with equipment manufacturers.

A work-plan for a second phase will propose the introduction of a last Cu interconnection level in the 0.25 micron modules stabilised by ADEQUAT.

COIN should be considered as a satellite project of ADEQUAT. In parallel with the COIN project, ADEQUAT will continue to evaluate new aluminium alloys with improved electromigration and stress migration characteristics. This would allow a comprehensive comparison of interconnect performances for Cu metallisation and for alternative Al alloys. The Joint Logic Project, in which all the major European IC manufacturers have joined forces, will be the main beneficiary of this dual approach. Furthermore, all the industrial partners will transfer know-how for the development of future 0.18 micron CMOS technology. Other fields of exploitation arc products in bipolar or smart power semiconductor technology, where the use of copper metallisation would already be beneficial.


CONTACT POINT

Dr J. Torres
CNET
Chemin du Vieux Chêne, BP98
F - 38243 Meylan
tel: + 33/ 76 76 41 41
fax: + 33/ 76 90 34 43

Participants

GRESSI - F - C
SIEMENS - D - P
MHS - F - P
TU CHEMNITZ - D - P
TU DRESDEN - D - P
U. HANNOVER - D - P
NMRC - IRL - P
INPG/LMPG - F - A


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COIN - 9021, December 1993


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html version of synopsis by Nick Cook