Cost-Effective High-Performance Packaging for Electronic Systems


CHIPPAC - 8248

Keywords packaging, MCM, KGD, BGA


Start Date: 15-NOV-93 / Duration: 30 months

[ contact / participants ]


Objectives and Approach

A cost effective packaging, an essential factor for successful access to the market of electronic systems, must be developed jointly by semi-conductor manufacturer, material supplier and the system manufacturer. Its implementation into manufacturing requires a substantial investment in technology development.

The technologies which will be developed as part of the CHIPPAC project will allow efficient packaging (performance and cost) of large VLSIs, dissipating 10 W and more. The work of the consortium will define, build and characterise single chips packages (SCP) and multichip modules, including techniques for connecting the chips to the packages and substrates. The Known Good Die supply necessary for the MCMs growth is addressed. The bonding techniques cover all currently used bonding methods: wire bonding, TAB and flip chip. These techniques will not only be pushed to further refinement, but a significant effort will be directed towards investigation of assembly yields, inspection and repair methods for the needs of practical exploitation. Different options of construction will be developed and characterised as demonstrator workpackages: ceramic multilayers (SCP-Cs and MCM-Cs) and laminated organic based multilayers (SCP-Ls and MCM-Ls). This variety of developments in one project will thus cover a whole range of application cases. It will also enable the comparison of different technical solutions including their cost/performance figures of merit.

The insertion of the packages and modules into the systems is also taken into account through the development of high density assembly processes (dense bonding to the boards) and through the development of high performance connectors with an emphasis on the rapidly rising surface area connections (BGA, LGA).

The technical benefits of the project will be improvements in functional integration, packing density, high speed performance, thermal management and reliability together with reduced power consumption. Cost advantages will arise not only form the selection of materials and processes specifically for that purpose but also from the direct consequences of using smaller and lighter packages, chassis, heatsinks, etc. and from improvements in production yield and maintainability.

Target applications of the project include telecommunications (network and personal systems), transport (navigation/location/traffic control) and computer.

The consortium, which includes partners with world leadership in packaging technology, will work to strengthen the positioning of Europe in this key sector of the microelectronics industry. The projects results will provide several innovate in technology and applications, namely:


CONTACT POINT

Dr K. Kurzweil
BULL SA
Rue Jean Jaurès
F - 78340 Les Clayes-Sous-Bois
tel: + 33/ 1-30807000
fax: + 33/ 1-30807833

Participants

BULL S.A - F - C
SGS-THOMSON MICROELECTRONICS - F - P
MIETEC SA - B - P
TELEFONICA INVESTIGACION Y DESARROLLO - E - P
IBM FRANCE - F - P
GEC MARCONI LIMITED - UK - P
BULL HN ITALIA SPA - I - P
NMRC - IRL - P
IBM DEUTSCHLAND INFORMATIONS
SYSTEM GMBH - D - P
FRAMATOME CONNECTORS FRANCE - F - P
IMC - S - P


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CHIPPAC - 8248, December 1993


please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook