Keywords 0.25 micron CMOS, 0.35 micron CMOS
Start Date: To be announced / Duration: 20 months
[ contact / participants ]
The rate of increase of packing density of logic ICs of the last two decades has been the same as that of DRAMs. System performance increases directly with device performance improvement, and thus there is a strong motivation for continuing the development of advanced devices. Since this development entered the deep sub-micron region, device design requires optimisation and trade-off between a multitude of constraints involving device performance, parasitics, power consumption, reliability and manufacturability.
The ADEQUAT project aims to develop new device structures and process modules for the 0.25 micron CMOS logic generation offering improved performance with acceptable reliability while still meeting the manufacturability constraints.
The ADEQUAT consortium coordinates and harmonises the effort of eight partner teams across Europe (four from R&D centers and four from industrial development groups) and of several associated partner teams, mainly from universities. The synergy between R&D centers and the teams from the IC manufacturers assures that the transit time from the conceptual phase to the exploitation phase is minimised. This unique strategy is embedded in a dedicated work package on Industrial Transfer.
The overall project will concentrate on the early development and demonstration of the feasibility of the individual process modules for 0.25 micron CMOS technology.
In the first phase (project 7236), this effort is being carried out in the framework of 0.35 micron lithography, and the feasibility of major process steps is demonstrated by the fourth quarter of the first year of the project. This will lead to the optimisation and stabilisation of advanced 0.35 micron modules in a 0.5 micron CMOS technology by the end of this first phase.
The work plan also includes an intermediate industrial transfer of 0.35 micron front-end modules by end 1993 and of back-end-of-the-line modules in 1994.
The core of this project is this work on the process modules which involves the study of scalability and of the impact on electrical characteristics of the implementation of smaller design rules; the development of process sequences with more latitude (eg for lateral and well isolation and the MOST gate stack); the development of new device architectures and novel interconnect schemes: and the demonstration of the feasibility of the newly developed modules (this will be in an 0.5 micron CMOS environment as far as the 0.35 micron modules are concerned).
The possible benefits resulting from the new modules (eg in terms of performance enhancement, process margin or process control improvement or better productivity) will be analysed and reported, leading to individual decisions on the process module transfer by the manufacturers. Several examples of choices illustrating this optimisation process are already available.
In close collaboration with the module development, work in Basic Steps develops alternative solutions for dielectrics, junctions and conductors which should provide sufficient room for scalability towards the 0.25 micron technology generation.
The supporting work on Patterning for the process modules is on the development of the necessary lithography and etching tools, putting emphasis on deep-UV lithography.
In the accompanying work package Modelling advanced physical models are being developed for the simulation of both process steps and electrical device behaviour and work in Reliability and Diagnostics addresses tools needed for the quantitative evaluation of process and device aspects in the sub-micron range and which will be implemented through studies of device reliability degradation mechanisms.
The ultimate aim of these process developments is to improve circuit performance and to build new products inaccessible with existing technologies. The applications to be served and the resulting performance requirements are addressed by the JESSI Joint Logic project (7363), in which all the major European IC manufacturers have joined forces, and with which ADEQUAT has established a concurrent engineering relationship. This link has provided direction and resulted in a wider visibility of the boundary conditions set by other disciplines on this type of development work.
Furthermore, all the industrial partners will transfer know-how and exploit ADEQUAT modules in their pilot line environment for the development of CMOS logic production processes.
A work-plan for a second phase (project 8002) provides the extension into the 0.25 micron regime, leading to the stabilisation of 0.25 micron modules in a 0.35 micron environment, under the same guiding principles.
For the duration of this second project emphasis will be placed on the front-end 0.25 micron modules.
Mr R. De Keesmaecker
B - 3001 LEUVEN
tel: + 32/ 16-281-326
fax: + 32/ 16-281-576
IMEC VZW - B - C
GRENOBLE SILICIUM SUB MICRONIQUE - F - P
PHILIPS CONSUMER ELECTRONICS - NL - P
SGS-THOMSON MICROELECTRONICS - F - P
SIEMENS AG - D - P
PLESSEY SEMICONDUCTORS - UK - P
FRAUNHOFER INSTITUT FUER
FESTKORPER TECHNOLOGIE - D - P
TECHNISCHE UNIVERSITEIT DELFT - NL - P
CENTRE NATIONAL DE LA RECHERCHE
SCIENTIFIQUE EPST - F - A
UNIVERSITY OF SURREY - UK - A
UNIVERSITA DI PARMA - I - A
UNIVERSITY OF WARWICK - UK - A
UNIVERSITA DI PISA - I - A
UNIVERSITA DI BOLOGNA - I - A
CNRS-LAAS EPST - F - A
TECHNISCHE UNIVERSITEIT EINDHOVEN - NL - A
SGS-THOMSON MICROLECTRONICS - I - A
TECHNISCHE UNIVERSITÄT WIEN-IAIS - A - A
SIEMENS AUSTRIA - A - A
CNR-ISTITUTO LAMEL - I - A
NATIONAL RESEARCH CENTRE FOR
SCIENTIFIC RESEARCH DEMOKRITOS - GR - A
LEPES-CNRS-GRENOBLE - F - A
UNIVERSITEIT TWENTE - NL - A
NMRC - IRL - A
CNM - E - A
EPFL LAUSANNE - CH - A
VTT - SF - A
ADEQUAT - 8002, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook