Neurocomputing

GALATEA II - 7807

Keywords ASICs, neural networks, OCR, parallel architectures, silicon compilers, surface-mounted device assembly, vision systems

Start Date: 01 January 1993 / Duration: 15 months / Status: ongoing

[ contact / participants ]

a hardware and software environment for developing neural network applications and its validation on selected industrial applications

Objectives and Approach

The project contains the last phase of the work programme of the GALATEA project (5293) and deals with:

• production of the dedicated chip L-Neuro 2.0 for small sized neural networks
• full integration of all the components of the system
• production of a dedicated OCR chip using the silicon compiler methodology and integration of the OCR application onto this chip
• on-line integration (with cameras) of both industrial vision applications with the project hardware

CONTACT POINT

Catherine Simon
Thomson-CSF/DOI
160 Blvd. de Valmy
BP 82
F-92704 COLOMBES CEDEX
tel: +33 1 4130 3597
fax: +33 1 4130 4918
telex: 616780 THOM F

Participants

Coordinator
Thomson-CSF/DOI [F]
Partners
Computer Technology Institute [GR]
Cram [I]
Inesc [P]
Mimetics SA [F]
Philips [F, NL]
SGS-Thomson Microelectronics SRL [I]
Siap Sistemi SPA [I]
Siemens AG [D]
University College London [UK]
Associate Partner
INPG [F]

GALATEA II - 7807, December 1993

please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook