Joint Logic Project


JLP - 7363

Keywords sub-micron digital CMOS, sub-micron analogue CMOS, sub-micron low-voltage CMOS


Start Date: 01-APR-92 / Duration: 36 months

[ contact / participants ]


Objectives

The JESSI JLP is one of the projects proposed in 1991 and 1993 by the JESSI organisation for Community funding. The project has already been funded for the 18 month start-up-phase of JESSI during 1990-91 (project 5080), and also incorporates the activities of project 5048 (ACCESS). For the main phase of JESSI, which started in 1992, the consortia have proposed a three-year project which combines the resources of the eight major European semiconductor companies and two of the leading research institutes. According to Dataquest, these companies together took a 9.1% share of the world semiconductor market in 1991.

In JESSI, being a set of project clusters which together tackle not only the development of key process technologies but also the development of the manufacturing equipment and applications, the Joint Logic project occupies a central position as it is strongly connected and to a large extent driven by the user-defined applications projects (known as "Europrojects"). The timetable of the project has been coordinated with the technology requirements of these key applications drivers, and in particular with the "Mobile Radio", "Broadband Communications", "HDTV", "Digital Audio Broadcasting", and "Automotive Safety Electronics" activities. The partners in these latter projects are funded by their respective national governments in the context of the EUREKA programme.

The JLP project also guides the work undertaken by European R&D centres on next-generation 0.25 micron CMOS technology (project 7236/8002).

In its initial phase, the emphasis was on the development of a core 0.7 micron CMOS technology and on functional options (non-volatile memories, analogue) in a 1 micron technology.

Today, the JLP project is focussing on the development and qualification of a state-of-the-art CMOS process with a feature size of 0.5 microns and on analog and low-voltage options in the 0.7 micron technology generation. These processes are targeted on a very broad range of applications (including high-performance digital logic circuits as found in consumer and computer products, and low-power and low-voltage chips for use in portable equipment), as well as having the capability to combine analogue functions typically used in the telecommunication and automotive sectors of the market.

The project generates the basic 0.5 micron CMOS technology by the joint effort of the partners in a subproject dedicated to the development of the basic process steps; develops various functional options to be added to the core process (activities on analogue and low voltage are organised in two separate subprojects); integrates the core technologies into processes for specific exploitation areas and demonstrates and qualifies the technology by means of several company-specific demonstrators.

The project also announced the availability for the European users, external to the project, of this 0.5 micron CMOS based on aggressive set of design rules and offers further access to this technology via existing channels such as Eurochip or Chip Shop in particular for universities or SMEs, and is now exploiting the 0.7 micron generation in volume production.


CONTACT POINT

Dr Mart Graef
Philips Semiconductors BV
Building WAG
PO Box 80.000
NL - 5600 JA Eindhoven
tel: + 31 / 4074-4600
fax: + 31 / 4074-3390
telex: 35000 PHTC NL

Participants

PHILIPS INTERNATIONAL BV - NL - C
ES2 SA - F - P
MATRA-MHS SA - F - P
GEC- PLESSEY SEMICONDUCTORS LTD - UK - P
SIEMENS AG - D - P
TEMIC - TELEFUNKEN ELECTRONIK GMBH - D - P
SGS-THOMSON MICROELECTRONICS - I/F - P
MIETEC NV - B - P
CNET-SEPT - F - A
IMEC VZW - B - A


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JLP - 7363, December 1993


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html version of synopsis by Nick Cook