Architectural Methodologies for Advanced Testing of VLSI Systems


ARCHIMEDES - 7107

Work Area: Algorithms for Design Methodologies for Complex Circuits and Digital Optical Systems

Keywords VLSI systems testing, testable architecture synthesis, IC defects-based testing, BIST


Start Date: 24 July 92 / Duration: 36 months / Status: running

[ participants / contact ]


Abstract ARCHIMEDES aims to bridge the gap between two apparently opposing trends in the VLSI design sphere: i) designing circuits from higher and higher levels in order to take advantage of the very large number of devices made available by the progress of technology, ii) efficient testing based on IC defects fault models, which lead to non-affordable times if testing is based on conventional test pattern generation for large designs. To this end, multiple testing methods targeted to multiple types of ICs are being developed using design for testability techniques.


Aims

ARCHIMEDES aims to answer the following questions:

No research is expected to be done on existing mature testing techniques. Advances in each area will cross-fertilised in order to obtain a global solution for the architectural synthesis of testable circuits.

Approach and Methods

Test pattern generation has now attained a good level, and professional CAD software exists to deal with quite large (though limited) parts of designs. Most parts can be dealt with by making them testable at the synthesis stage. To answer the questions raised above, ARCHIMEDES brings together experts on several individual testing methods, approaches and types in order to seek a global solution.

Specific areas of investigation include architectural synthesis, realistic analysis and innovative test techniques.

Progress and Results

Results have been obtained in many different facets including the following: target structures for datapathes and controllers to be synthesised for off-line testability, regular structures like PLAs designed for on-line testability, the design of optimal analysers and the design of deterministic generators based on LFSROM; emphsis on BiCMOS for defect analysis, on bridging faults for layout design for testability, on analogue and mixed signal for fault modelling; the use of current testing for analogue and mixed-signal circuits, the designs of analogue checkers for on-line testing, the design of built-in current sensors.

Potential

Research results are expected to contribute to the advance of the state of the art in many facets of testing. Applications are foreseen in industrial advanced products, making a contribution to the three major features governing the success or the failure of an electronic product in the market place: innovation, time-to-market, and quality.

Latest Publications

Information Dissemination Activies

Two open workshops have been organised:


Coordinator

TIMA, Institut National Polytechnique de Grenoble - F
avenue Felix Viallet 46
F - 38031 GRENOBLE CEDEX

Partners

Universität Hannover, Institut fur Theoretische Elektrotechnik - D
Universität Siegen, Fakultat fur Elektrotechnik und Informatik - D
Universidad Politecnica de Catalunya, Barcelona - E
Universite de Montpelier II-LIRMM - F
Universita di Bologna - I
INESC, Lisboa - P

CONTACT POINT

Dr. B. Courtois
tel +33/76 57 46 15
fax +33/76 47 38 14
e-mail: courtois@archi.imag.fr


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ARCHIMEDES - 7107, August 1994


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html version of synopsis by Nick Cook