Integrated Circuit Design for Signal Processing


INCIDE - 6904

Work Area: Algorithms for Design Methodologies for Complex Circuits and Digital Optical Systems

Keywords DSP ICs, self-timed systems, micropipelines, synchronous/asynchronous circuits, biCMOS design


Start Date: 24 July 92 / Duration: 36 months / Status: running

[ participants / contact ]


Abstract Research for circuit design for signal processing is pursued in two areas: in order to overcome synchronisation problems on the chip, aynchronous circuit concepts are discussed in detail and test vehicles implemented; and CMOS versus BiCMOS is studied in using various macro building blocks.


Aims

The INCIDE Working Group focuses first on new circuit design concepts which implies more granular on-chip communication scheme, and their applicability to the implementation of signal processing algorithms. Within INCIDE it is aimed to develop and explore design concepts based on self-timing, micropipeline architectures, and asynchronous data processing techniques. In order to achieve competitve circuit design concepts, questions related to design automation and testability are taken into account as well.

Secondly, new BiCMOS circuit concepts will be studied through realising macro building blocks, in order to evaluate the potential of BiCMOS versus CMOS.

Activities

Within INCIDE a team was established which concentrates on asynchronous circuit concepts. Currently researchers located at the University of Ulm (Germany), Abteilung Allgemeine Elektrotechnik und Mikroelektronik, and at the Technical University of Berlin (Germany), Institut fuer Mikroelektronik, are involved. Prof. T. G. Noll from RWTH-Aachen (Germany) and Prof. D. Mueller from the Technical University of Chemnitz (Germany) are planning to participate in these activities. Besides the exchange of ideas and solutions cultivated by the members of the Group and the team, a cooperation with members of the ACID Working Group (7225) was brought about, eg visits and presentations at Workshops held by ACID-WG.

The BiCMOS group met at a Workshop on BiCMOS design on February 5th 1993 at Phillips laboratories in Eindhoven. New circuit concepts were presented and discussed. The next meeting is planned for the end of this year in Pavia.

Progress and Results

Concerning the design of asynchronous circuits, low level circuit design and building-blocks in micropipeline architecture were studied. Improvements have been achieved in the design of handshake circuitry. Major properties of the developed circuits are relaxed timing constraints and therefore improved reliability.

Some efforts were made to apply design automation techniques, ie standard cell methodology, to the design of asynchronous circuits. This led to the development of a standard cell library consisting of DCVSL functional cells and handshake circuitry, respectively. The well-known scan-path technique was introduced to assure for testability. Appropriate cells were designed and added to the library to allow for the implementation of scan-paths together with self-timed modules and building-blocks. Two self-timed test circuits, a serial/parallel multiplier and a Booth multiplier with scan-path were designed and are currently under fabrication.

Novel BiCMOS circuit concepts for high-frequency tunable filters and for an ECL to CMOS logic level converter have been developed.

Prototypes and test results are available.

Potential

Advanced concepts for asynchronous circuits, design automation, and design for testability are considered as a whole, in order to develop suitable solutions. These are fundamental prerequisites to bring new circuit design concepts into industrial use. First results will be presented to a broad audience on ESSCIRC 1993.

Latest Publications

Information Dissemination Activies

To promote the experience and results gained in the Group, conferences (eg ESSCIRC) and workshops are extensively used to present these research activities and new results to a broad audience. Besides this, a fruitful cooperation with ACID-WG is maintained.


Coordinator

Universität Ulm - D
Allg. E.-Technik und Mikroelektronik
Fakultät für Ingenieurwissenschaften
Postfach 4066
D - 89081 ULM

Participants

Technische Universität Berlin - D
Università di Pavia - I
Philips Research Laboratory - NL
Technische Universiteit Delft - NL

CONTACT POINT

Prof. Dr. H.-J. Pfleiderer
tel +49/731 502 4160
fax +49/731 543 12
e-mail: pfleider@rz.uni-ulm.dbp.de (EAN/X.400) / pfleider@DULRU51.bitnet (EARN/Bitnet)


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INCIDE - 6904, August 1994


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html version of synopsis by Nick Cook