Real-Time DSP Emulation System


RETIDES - 6800

Keywords digital signal processing (DSP), simulation


Start Date: 01-AUG-92 / Duration: 36 months

[ contact / participants ]


Objectives

The objective of RETIDES is to provide a platform for the fast prototyping of digital signal processing (DSP) systems. To this end, techniques, hardware and software will be provided to compile DSP algorithms, described in a high-level language, onto programmable parallel hardware for real-time execution.

The DSP emulation platform resulting from this work will be a turn-key integrated hardware and software CAD tool. It will play a crucial role in the design flow of integrated DSP systems, leading to:

RETIDES exploits results from project 97 and from SPRITE (project 2260), which resulted in the CATHEDRAL and PIRAMID silicon compilers for DSP ASICs, currently undergoing commercialisation as MISTRAL compilers in the DSP Station developed at EDC/Mentor.

Progress and Results

Within the first six months, a full specification of the DSP real-time emulation system has been achieved as planned.

Within less than one year after project start, a first product resulting from the RETIDES project has hit the market. In June 1993, Integrated Circuit Applications (INCA) released their new "Virtual ASIC II" logic emulation system with introduction at the Design Automation Conference - DAC '93.

The architecture of this system has been worked out within the RETIDES project and is fully prepared to provide the DSP emulation and accelerated simulation facilities RETIDES is aiming at.


CONTACT POINT

Mr J. van Ginderdeuren
Philips ITCL
DSP Laboratory
Interleuvenlaan 74-76
B - 3001 LEUVEN
tel: + 32 / 16390643
fax: + 32 / 16390600

Participants

PHILIPS INTERNATIONAL TECHNOLOGY
CENTRE LEUVEN - B - C
INTEGRATED CIRCUIT APPLICATIONS - UK - P
KATHOLIEKE UNIVERSITEIT LEUVEN - B - P
THOMSON-CSF - F - P
EUROPEAN DEVELOPMENT CENTRE - B - P


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RETIDES - 6800, December 1993


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html version of synopsis by Nick Cook