Keywords fault-tolerant architectures, parallel architectures, T805, T9000, transputers
Start Date: 01 August 1992 / Duration: 36 months / Status: ongoing
[ contact / participants ]
supporting extremely long executions of application code on existing parallel platforms with thousands of processors
The objective of FTMPS is to develop techniques and system software capable of accommodating component failures in massively parallel computers in order to permit extremely long executions of application code, where a real-time response is not required.
A transputer-based system, featuring redundant processor nodes, a fault-tolerant communications network architecture and an independent network of control processors provides the environment for the work.
The project examines:
Further information about FTMPS is available from the FTMPS home page <URL:http://osiris.parsytec.de:7591/project/rdpro.html>.
tel: +49 241 166-000
fax: +49 241 166-0050
Parsytec GmbH [D]
British Aerospace (Military Aircraft) [UK]
Katholieke Universiteit Leuven [B]
Universidade de Coimbra [P]
Universität Erlangen-Nürnberg [D]
Universität Paderborn [D]
FTMPS - 6731, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook