Advanced Test Generation and Testable Design Methodology for Sequential Circuits

ATSEC - 6575

Work Area: Algorithms for Design Methodologies for Complex Circuits and Digital Optical Systems

Keywords IC test, CMOS test, automatic test pattern generation, fault simulation, overcurrent test, sequential circuit ATPG

Start Date: 1 November, 1992 / Duration: 36 months / Status: running

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Abstract ATSEC is developing methods and algorithms for efficient and reliable automatic test generation in large sequential circuits. The approach taken covers static as well as dynamic fault models and overcurrent effects in order to account for the real fault behaviour of advanced CMOS technologies. To meet system design demands, also high-level behavioral test strategies are developed.


With emerging submicron CMOS technologies not only the complexity of circuits is increasing rapidly, but also the fault behaviour is shifting towards dynamic rather than static faults. For cost reasons, the overhead required for testable design has to be minimised, which in turn requires much more powerful tools for generation and validation of test patterns. The basic aim of ATSEC is to bring sequential ATPG techniques closer to industrial application by adding handling capabilities for non-trivial circuits and dynamic fault models as well as non-trivial clocking schemes. Also overcurrent-based testing, which is an essential step towards zero-defecttesting for safety-critical applications, will be supported.

Approach and Methods

A modular approach is used which supplies rapid test generation for static fault model, also for distributed clocking schemes on one hand, and ATPG for dynamic faults and mixed-level circuits on the other hand.

These aspects of "base line" ATPG tools are covered by Univ. of Duisburg and GMD, which also provides a mixed-level sequential fault simulation tool. Extensions towards ATPG for bridging faults and static overcurrent (Iddq) testing are also developed. Special tools providing test generation and even diagnosis capabilities for delay faults are developed by University of Twente and LIRMM (Montpellier), respectively.

At the system level, test generation based on behavioural descriptions is a necessity for very complex systems. ATPG for systems is developed by Politecnico di Torino; and a link between high-level behavioural and lowlevel structural ATPG is to be established. As an associate partner, KIHWV Oostende evaluates prototype tools on realistic example circuits. Besides this work, KIHWV, GMD, and the Slovak Technical University of Bratislava cooperate in the development of circuits and methods supporting static overcurrent (Iddq) testing in CMOS circuits.

Progress and Results

During the first year of the project mostly basic algorithms for the individual tasks were developed and implemented.

At GMD, the combinational version of the MILEF test pattern generator was developed and expanded into a first sequential version. This first version of the baseline ATPG tool, presently supporting stuck-at faults and Iddq test, was tailored to accommodate the "special purpose" ATPG tool developed a Twente. Also a mixed-level sequential version of the FEHSIM fault simulator was implemented. At the University of Twente, a first version of a delay fault test pattern generator was developed. LIRMM (Montpellier) has developed and implemented a tool for delay fault diagnosis in combinational logic.

At Politecnico di Torino, a method for system level ATPG based on an extended finite-state-machine notation was developed and implemented.

GMD has also done basic investigations on the definition and test of bridging faults. GMD's programs MILEF and FEHSIM were evaluated at KIHWV (Oostende). The distribution of prototypes to academic and industrial users has begun.

In a cooperative approach, KIHWV Oostende, Slovak Technical University and GMD designed several versions of on-chip (built-in) current monitoring circuits, which will be implemented and evaluated in the next months.


The expected result is a powerful modular test generation system. The underlying concept is to provide a high performance ATPG based on simple fault models, which can be supplemented by more refined application-specific functions such as advanced fault models upon user demand. The final objective is to have such tools operation in combination with other software and within framework based on CFI-standards.

The expected programs will support European industries in their efforts to develop reliable and testable electronic systems at the lowest possible cost.

Latest Publications

Information Dissemination Activies

GMD has edited a volume containing recent publications by ATSEC partners and an information summary on ATSEC. This material is distributed to industries.

GMD has started to supply prototype tools (MILEF, FEHSIM) to academic members of other ESPRIT projects and selected industrial users.

MILEF and FEHSIM will be demonstrated during the EURO-DAC'93 Conference (Hamburg, Sept. 1993), FEHSIM was demonstrated at the 30th DAC in Dallas.

A first ATSEC workshop will be held at Torino in late Sept. 1993, where potential users of ATSEC results may attend.


Institute SET
Schloß Birlinghoven
D-W - 5205 ST. AUGUSTIN 1


Universität Duisburg - D
Université de Montpellier II - LIRMM - F
Politecnico di Torino - I
Universiteit van Twente (MESA Research Institute) - NL
University of Oxford - UK

Associate partner

KIHWV, Oostende - B


Dr. H.T. Vierhaus
tel +49/2241-14-2633
fax +49/2241-14-2242

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ATSEC - 6575, August 1994

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html version of synopsis by Nick Cook