Fail-Safe Semicustom Design


FASED - 6378

Work Area: Fail-safe Semicustom Circuits

Keywords semicustom design, fail-safe circuits, self-checking circuits, redundancy, reliability


Start Date: 1 September 92 / Duration: 36 months / Status: running

[ participants / contact ]


Abstract FASED is studying the design of self-checking and fail-safe circuits using standard cells, predefined blocks, gate arrays and field programmable devices, as well as techniques for high availability in self-checking semicustom circuits. Topics include theoretical background, fault modelling, redundancy techniques, design rules, and CAD tool requirements for fail-safe circuit design.


Aims

The objectives of the FASED Working Group are the study of fail-safe circuits that are designed and fabricated by using the semicustom design methodology. This may lead to significantly lower design times and costs as compared to current full custom chips. To achieve higher circuit availability, the use of redundancy techniques in fail-safe circuits is investigated.

Topics of interest to the group include: fault modelling in semicustom circuits, theory of self-checking and fail-safe circuits, CAD algorithms for the automatic generation of self-checking modules, self-testing techniques and built-in test, reliability and failure mechanisms, and redundancy techniques. The use of the semicustom design style could greatly enhance the applicability of fail-safe circuits to industrial electronics, and provide low-cost, high-reliability solutions in safety-critical applications.

Activities

The group's expertise ranges from semiconductor fabrication through the design of fail-safe circuits to redundancy techniques. The group utilises this expertise to perform research in the area of fail-safe semicustom design and related areas such as testability as part of Esprit projects and other national and international projects. While some topics require participation of all partners, some specialised topics are studied in bilateral fashion. The group furthers its objectives by topical meetings in the area of semicustom design techniques, self-checking and fail-safe circuit design, and reliability aspects. Yearly internal workshops and exchange visits facilitate direct information exchange between all participating scientists. The group plans to organise an international workshop in the field of fail-safe circuits, and participates in workshops of other related ESPRIT consortia.

Progress and Results

Since the start of the working group in September 1992, the partners have made progress in several areas of fail-safe semicustom design. In the area of fault modelling and test generation, extended fault models for test generation were considered which are required to assure proper operation of semicustom circuits. This results in more complicated tests and test pattern, eg, two-pattern tests for stuck-open and delay faults.

The generation and application of such enhanced tests in scan-path based circuits was optimised. Short circuits within a chip can be detected by measurements of the quiescient current. High-speed test methods with off-chip and on-chip current monitoring were developed and will be optimised further.

One type of semicustom circuits are the Programmable Logic Devices (PLDs). They are becoming more popular since they can provide great flexibility together with fast implementation. One interesting feature of this kind of device is the fact that they can be reconfigured. This characteristic can be used to implement self-checking circuits that can be reconfigured following a fault detection. Presently, the test of Configurable Arrays of Logic (CALs) (a family of dynamically reconfigurable PLDs) is studied. Powerful test algorithms have been developed that ensure 100% single stuck-at fault coverage. Additionally, the necessary conditions for a CAL to be C-testable were derived. Future work includes the development of built-in self-test strategies and the design of self-checking logic blocks.

For highly complex circuits up to wafer-scale integration, fault-tolerant architectures and testing techniques were devised. Chips design utilising these techniques was investigated, including a chip set for the Hough Transform, fault tolerant convolvers, fast multipliers, and neural network structures.

Potential

In the short term, the research carried out by the group will provide better understanding in the area of failure mechanisms of semicustom circuits, which can contribute directly to more reliable integrated chips by appropriate modification of design style. The group's work in fail-safe semicustom circuits can, in the long run, provide a large community of IC-Designers with both the know-how and design methods to design and implement safety-critical application-specific circuits; currently, such designs are restricted to very few projects because the necessary full custom design style requires long design times and high manpower efforts. With the addition of redundancy to fail-safe semicustom circuits, their life time and their reliability can be enhanced.

Latest Publications

Information Dissemination Activies

The members of the working group have published their results extensively at national and international conferences, and will continue to do so. For 1994, a workshop on various aspects of fail-safe semicustom circuits is planned.


Coordinator

Institut für Mikroelectronik - D
Allmandring 30A
D - 70569 STUTTGART

Participants

INPG/TIM3 Grenoble - F
Politecnico di Milano - I

CONTACT POINT

Dr. T. Schwederski
tel +49/711-685 5860
fax +49/711-685 5930
e-mail: schwederski@mikroelektronik.uni-stuttgart.dbp.de


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FASED - 6378, August 1994


please address enquiries to the ESPRIT Information Desk

html version of synopsis by Nick Cook