Formal Design and Correctness Verification of Synchronous and Asynchronous Digital VLSI Systems


CHARME-2 - 6018

Work Area: Algorithms for Design Methodologies for Complex Circuits and Digital Optical Systems

Keywords formal verification, hardware verification, correct design, theorem proving, correctness verification


Start Date: 1 September 92 / Duration: 36 months / Status: running

[ participants / contact ]


Abstract CHARME-2 will study novel methods for guaranteeing the correctness of future complex hardware designs. Emphasis will be placed on the correct modelling and specification of hardware as well as on formal design and verification methods. The group's focus will be both automatic and user-guided formal verification methods covering design abstraction levels from the transistor switch level, gate level, structural register transfer level and behavioural register transfer level up to algorithmic specifications. The work builds on the results of CHARME 1 (3216).


Aims

Functional verification is one of the bottlenecks of VLSI-based system design. For economic and industrial reasons, the design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is still done mainly through the simulation of a limited set of test cases. This does not guarantee correctness. Formal verification methods, on the other hand, are analytic, and avoid the simulation of specific input stimuli. They have the potential to guarantee the correctness of implemented circuits with respect to their specifications for all allowable input stimuli.

Fundamental problems still have to be formalised, and efficient domain-specific solutions still need to be found in order to be able to bring formal verification into use for realistically sized applications.

Activities

The group will address the following topics: efficient basic verification techniques; efficient and automatic verification tools for both synchronous and asynchronous designs; methodologies for designing verifiable circuits; symbolic state-space exploration techniques; verification from lower level (gate and transistor switch) up to higher levels; specification formalisms and provable subsets of HDLs; formal verification from industry-standard VHDL language; integration through a common data model and a common verification methodology; and evaluation of progress in verification technology and methodology through applying both to real chip designs.

A multi-disciplinary approach is required. The combination of universities and an electronics research institute gives the appropriate balance between a theoretical approach and one focusing on applied methods. The group will further its objectives through its own internal contact network which will involve meetings of partners active in the above topic areas. The group may organise international workshops in the field of formal hardware design and will participate in workshops involving formal methods and design methodology related topics.

Potential

This working group aims to enhance the potential for future technological breakthroughs by identifying novel techniques for the formal verification of the complex VLSI systems that will be required by the European IT industry. The progress of this working group will be regularly presented at international conferences and workshops and in publications.


Coordinator

IMEC vzw - B
Kapeldreef 75
B - 3001 LEUVEN

Participants

Johan Wolfgang Goethe Universität, Frankfurt - D
IMAG-ARTEMIS, Université Joseph Fourier - F
Université de Provence - F
Politecnico di Torino - I
University of Strathclyde - UK

CONTACT POINT

Prof. L. Claesen
tel +32/16-281203
fax +32/16-281515
e-mail: claesen@imec.be


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CHARME-2 - 6018, August 1994


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html version of synopsis by Nick Cook