Keywords knowledge-based systems, logic programming, constraint logic programming
Start Date: 01-JAN-91 / Duration: 48 months
[ contact / participants ]
The CHIC project is designed to accelerate the exploitation of Constraint Logic Programming (CLP) in industrial environments. Recent advances in CLP, in particular the CHIP system developed at the European Computer Industry Research Centre (ECRC), have given Europe a significant lead in technology suited to large combinatorial problems, such as those confronted in production management, VLSI design, financial systems, logistics and network management. The three industrial partners (Bull, ICL LTD and Siemens) have absorbed the CHIP system into their own product lines and are currently seeking to enhance and extend their applications.
The basic strategy of the work programme is to take the CHIP system as the kernel language and divide the enhancements into short, medium and long-term goals. This is intended to maximise the range of successful products while minimising the risks. Applications which are certain to emerge in the short term will be pursued in the fields described above.
The long-term aspirations will be targeted towards engineering a successor to CHIP. Here the risk factor is not negligible. This will be partially offset by the medium-term objective, which is to extend the existing CHIP system to new problem areas such as planning, the design of communication protocols, and configuration problems. The aim is to seek a substantial increase in value added to CHIP while containing the risks.
To tap a representative cross-section of potential users of CLP technology, a user interest group will be formed under the provisions of the European Economic Interest Grouping (EEIG). The six founder-members of the user group will be represented in the Consortium as associate partners and will help focus the direction of the work-programme towards the marketplace.
The users group is pursuing application experiments using existing CLP platforms. New requirements have been identified for the development of the future platform: temporal reasoning, design and verification of finite-state systems, new computation domains such as symbolic and non linear constraints, and new computation rules.
A list of good practices for programming with CLP has been set up and will lead to a full methodology (discussions with the PRINCE project have started on this topic). Tools for the programming environment and the development of the new CHIC platform are in progress.
BULL, ICL LTD and SIEMENS will incorporate enhancements and new features developed within the project in their respective home products already on the market (CHARNE, DECISION POWER, SNI-PROLOG).
SIEMENS will exploit the results of the project for its own internal activities in VLSI design, communication systems and knowledge-based design techniques.
The members of the user group, after experimentation on selected applications, have started to exploit and disseminate the technology in their own area of interest.
Dr Eric Tiden
Postfach 830 953
D - 8000 MÜNCHEN
tel: + 49/ 89-636-45802
fax: + 49/ 89-636-42284
telex: 52109 11 SIE D
SIEMENS AG - D - C
BULL SA - F - P
ECRC GMBH - D - P
IMPERIAL COLLEGE OF SCIENCE,
TECHNOLOGY & MEDICINE - UK - P
AIS SPA - I - A
ONERA-CERT - F - A
RENAULT RNUR - F - A
ICL LTD - UK - A
ON CAMPUS TECHNOLOGY SL - E - A
CMSU - GR - A
AVIONS MARCEL DASSAULT - F - A
BRAGHENTI & C. INDUSTRIA
TESSILE SPA - I - A
COSYTEC - F - S
CHIC - 5291, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook