Joint Logic Project


JLP - 5080

Keywords 0.5 micron CMOS


Start Date: 01-JUN-90 / Duration: 18 months

[ contact / participants ]


Objectives and Approach

The Joint Logic Project is part of the seven-year JESSI technology programme ("Green Book"). The project is subdivided into a number of phases, as shown below.

Period       Phase    Objective                 Project no.
6/90-12/91   JLP-1    0.7 micron CMOS logic        5080
                      1.0 micron options
1992-94      JLP-2    0.5 micron CMOS logic        7363
                      0.7 micron options
1995-96      JLP-3    0.35 micron CMOS logic
                      0.5 micron options

The objective of the Joint Logic Project was to develop the powerful CMOS processes required to improve the capability of European electronic product manufacturers to offer competitive products on a timely basis.

The objective in the first phase was the demonstration, by each company, of the capability of a 0.7 micron basic logic process, and all subprojects contributed to solve technical problems associated with this objective. Each company provided a company-specific demonstrator in order to verify the competitiveness of the process for specific applications.

A second objective was to produce and measure first silicon for various functional options, such as low-power non-volatile memories in 1.0 micron technology, and analogue logic in 1.0 and 0.7 micron technologies.

In addition, these CMOS processes (basic and options) may serve as an input for high performance BICMOS processes, in which high-performance bipolar is combined with sub-micron CMOS.

A third objective was the generation of a first set of target design rules for a 0.5 micron core logic technology.

Progress and Results

The major objective of project 5080 was the demonstration, by each company, of the capability of a 0.7 micron logic CMOS technology. This was done according to plan. Demonstrators have been made by all partners, in most cases incorporating a common 0.7 micron test module, and qualification of 0.7 micron technology is in progress at the various sites.

Both Philips and Siemens produced first silicon of their 3-layer metal demonstrator with excellent performances.

Test procedures for test chips and demonstrators are implemented, and a scribe line test insert was designed and distributed as GDSII tape among the partners. Commonality on characterisation procedures, reliability procedures and parameter definition was assessed, and new common procedures on reliability measurements of dialectrics and metallisation patterns were created. A complete synthesis on device optimisation was generated.

Several processing techniques and process problem areas were evaluated, compared and optimised or improved, which was often done in cooperation with other ESPRIT or JESSI projects. Major improvements were encountered in the multi-level metallisation processes and the isolation methodology.

The most important impact of the project on the 0.7 micron CMOS development at the different sites was the reduction in development time by sharing development results between the partners, and the improvement of process performance by comparison of electrical results.

Progress was also achieved with regard to the activities on functional options, and common process flow was defined for the 1.0 micron non-volatile memory option of Philips and Siemens. First silicon for these processes was produced, and the process is characterised by the process acceptance of a 6 kbit EEPROM at Siemens and a 64 kbit page EEPROM at Philips; both are suitable for embedding in 1 micron CMOS logic products. A first draft was generated of a common NVM process to embed non-volatile memories in standard 0.7 micron CMOS logic products.

Qualification of the 1.0 micron analogue process was realised by SGS-Thomson, and the process is under qualification at several other partners' sites. Several process improvements have been introduced, and matching performance and linearity of analogue components were intensively characterised. A process flow for a 0.7 micron analogue process was defined.

The various process architectures for 0.5 micron digital CMOS were compared, and a first draft set of design rules generated.

A common demonstrator of a multi-chip module in a low-cost quad flat package was developed. The technology for the assembly of a large die on a surface-mounted package was developed by SGS-Thomson, while Telefunken Electronik developed a multi-chip module mounted on a ceramic substrate. A leadframe was also designed and delivered. Processes were developed for die attachment of chip-on-silicon (COS) on the leadframe pad, for wire-bonding of the chips to the substrate and to the inner leads, and for moulding.

Two types of demonstrators were assembled: one with fully gold wire bonding, and the other with partially aluminium wire bonding (inner connections).

Exploitation

The process techniques are being exploited at several sites and the production is converted into these more performant sub-micron technologies. Several products are being fabricated and most of the new designs use the above technologies and methods, for instance:


CONTACT POINT

Mart Graef
PHILIPS INTERNATIONAL BV
Building WAG
NL - 5600 JA EINDHOVEN
tel: + 31/ 40-744600
fax: + 31/ 40-743390

Participants

PHILIPS INTERNATIONAL BV - NL - C
ES2 SA - F - P
GEC-PLESSEY SEMICONDUCTORS LTD - UK - P
SNI AG - D - P
TELEFUNKEN ELECTRONIK GMBH - D - P
STM-SGS-THOMSON
MICROELECTRONICS SRL - I - P
SGS-THOMSON MICROELECTRONICS SA - F - P
MIETEC NV - B - P
MATRA-MHS - F - P


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JLP - 5080, December 1993


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html version of synopsis by Nick Cook