Keywords ASICs, CAD, sub-micron processes, standard libraries
Start Date: 15-JUN-90 / Duration: 30 months
[ contact / participants ]
Following the completion of the first or definition phase of IDPS (projects 2270 and 2426), the second phase has now been completed.
IDPS aims to provide the industry with a state-of-the-art ASIC facility, including a common library, several design systems and a choice of five foundry services. Phases 2 and 3 of the project focus on sub-micron processes with 0.7/0.8 micron feature sizes which were available in time for commercial exploitation of the first IDPS results in the second half of 1992.
The key objectives set at the start of IDPS were:
The IDPS common library consists of standard cells (both digital and analogue), I/O cells and a family of module generators with agreed specifications. The partners have exchanged their generator contributions using the MODGEN package as the standard format. MODGEN consists of a procedural language and a compactor from Philips; the package is now supported commercially by Silicon & Software Systems. The IDPS library is supported by a number of CAD systems developed by the semiconductor manufacturer partners. These CAD systems consist of combinations of commercial tools and in-house developed tools and support state-of-the-art top down design flows.
The common library has been mapped into the individual processes of the four volume foundries which will offer a Quick Turnaround (QTA) service for prototypes. QTA is achieved by fine-tuning the processes and optimising the standard pilot lines, rather than by establishing expensive dedicated prototype lines. The fifth foundry, provided by ES2, offers a Very Quick Turnaround Time (VQTA) for prototypes. The VQTA foundry will make a dedicated effort to reach the final target of a four-week turnaround for standard complexity starting from a simulated netlist. The QTA foundries have a longer turnaround time than the VQTA, but with the same target of "right-first-time" designs and prototypes.
At the end of the formal project period the introduction of VHDL based synthesis is in full progress. VHDL behaviour models for simulation have been released. Introduction of backannotation in the VHDL domain is in development. Besides the original goal of netlist compatibility between the vendors, synthesis will provide a second method to transfer a design from one vendor and library to another.
The practical usefulness of the library, CAD and prototyping services will be shown by the IDPS demonstrators and test chips. User partners are orienting their demonstrators to products in their application areas. The vendor partners have shown examples of early exploitation of the results. In addition the vendors demonstrated netlist compatibility by each designing (ie, lay-out implementation and simulation) the same representative ASIC circuit example.
The complexity of ASICs has increased during the period of the IDPS project. The IDPS library and tools themselves allow the development of ASICs with a complexity of 1 to 2 million transistors. The design of a demonstrator of this complexity has started in year 3. Exploitation of IDPS results in the 0.7/0.8 micron process started in the second half of 1992, and improvements in turnaround time have been reported.
Exploitation has been demonstrated in 1993 by all partners. ES2 has accepted the responsibility to make the results available to small-volume ASIC customers. Other vendors will concentrate on internal use and larger customers.
Mr J. A. Van Nielen
Philips Semiconductors BV
NL - 6534 AE NIJMEGEN
tel: + 31/ 80-532468
fax: + 31/ 80-533602
PHILIPS SEMICONDUCTORS BV - NL - C
ROBERT BOSCH GMBH - D - P
BULL SA - F - P
STRUCTURES SA (ES2 SA) - F - P
SGS-THOMSON MICROELECTRONICS SA - F - P
MICROELECTRONICS SRL - I - P
SIEMENS AG - D - P
GEC PLESSEY SEMICONDUCTORS - UK - P
ICL LTD - UK - P
INFORMATIONSSYSTEME AG (SNI) - D - A
BELL TELEPHONE MFG CO NV - B - A
THOMSON COMPOSANTS MILITAIRES
ET SPACIAUX - F - A
UNIVERSITE DE PARIS VI - F - A
SILICON SOFTWARE SYSTEMS LTD - IRL - A
PIJNENBURG - NL - A
IDPS - 5075, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook