AD 2000 - 5056
Keywords analogue/digital-digital/analogue converters, CAD, analogue/digital systems
Start Date: 15-SEP-90 / Duration: 36 months
[ contact / participants ]
Objectives and Approach
The AD 2000 project aimed to develop advanced analogue/digital and digital/analogue converter architectures for low-cost CMOS technology capable of addressing the needs of emerging systems in the communications and consumer electronics industry. As projections of the world market for ASICs show, the portion of mixed analogue-digital systems will rise steadily. The realisation of high-performance low-cost converters is crucial for the successful development of commercially viable products. AD 2000's main goals are to stretch state-of-the-art performance limits with respect to speed and resolution, to improve CAD tools for architecture-level synthesis of converters, and to address functional testing and characterisation issues for improved quality control and reduced production costs.
Progress and Results
The following results were recorded:
- A CAD framework for the design of switched-capacitor delta-sigma modulators was developed consisting of a high-level synthesis tool, an advanced dedicated behavior simulator tool and an optimisation-based analogue cell design tool. This framework covers detailed noise analysis and simulation as well as innovative global statistical optimisation routines. The behavioural simulator uses FFT routines of previously reported TOSCA for signal analysis.
- A tool for the high-level synthesis of high-speed data convertors (CATALYST) was developed embedding a dedicated behavioural simulator and associated behavioural models. CATALYST is now being used to design high-speed data convertors architectures, including the capability for fully digital functional self-testing.
- The design of a reconfigurable analogue/digital and D/A convertor system operating at 10 million samples per second with 10-bit resolution has been completed and experimentally demonstrated. The chip is based on a two-step conversion architecture, both for analogue/digital and digital/analogue conversion, and its functional testability can be accomplished using fully digital resources. Also in this area of high-speed analogue/digital conversion another chip has been developed and experimentally demonstrated based on sub-ranging R-string architectures and employing dedicated active compensation circuitry for reducing the effects of parasitic capacitances.
- A new calibration technique is proposed for resolution enhancement of high-speed analogue/digital convertors. This has been demonstrated for designing a 15-linearity digital/analogue convertor, with a resolution as low as 5 bit. This, in turn, has been employed for designing, under the CATALYST environment, a 3-stage pipeline analogue/digital convertor operating at 15 million samples per second with 15-bit resolution.
- For electricity metering applications, two prototypes of delta-sigma converters based on advanced cascade modulator architectures with optimised oversampling ratio figures have been completed and experimentally demonstrated. Advanced delta-sigma converters were also considered for high performance instrumentation applications, as demonstrated through the design and integrated circuit implementation of a 21-bit analogue/digital convertor.
- The design of a digital/analogue convertor operating at 75 million samples per second with 8-bit resolution has been completed and experimentally demonstrated. The circuit is based on current-mode processing techniques for fully compatibility with standard purely digital CMOS technology. Also contemplated in this class of conversion circuits using current-mode processing techniques was the design and experimental demonstration of a digital/analogue convertor operating at 50 million samples per second with 10-bit of resolution and which makes use of an innovative solution for speed enhancement with active parasitics compensation.
- Several high-performance building blocks have been developed for the various classes of data convertors developed in the project, particularly those requiring high-speed and high-linearity. These include highly linear buffers, wide bandwidth operational amplifiers and high-speed comparators.
Technology and know-how transfer has been exploited and accomplished concerning the following project results:
- It was demonstrated the portability of the CATALYST behavioural models into commercially available CAD packages.
- The reconfigurable analogue/digital and digital/analogue convertor chip has been incorporated into one partner's proprietary image processing system, where it replaces two parts which currently are only available from US manufacturers.
- The sub-ranging high-speed analogue/digital converter, together with its DAC counterpart, are being explored for applications in radiocommunication front-ends.
- The sigma-delta analogue/digital convertors for electricity metering applications has been transferred to a system manufacturer under the framework of an early exploitation agreement.
- The very high-performance (21-bit) delta-sigma analogue/digital convertor is being exploited by one industry partner for high-performance instrumentation applications.
- The high-speed current-mode digital/analogue convertors are being considered for telecommunications front-end applications, including radio and sattelite direct digital synthesis.
- The high-performance components developed as building blocks for the several analogue/digital and digital/analogue convertors demonstrators are themselves high-value exploitable results. It is expected that some of these components can be transferred to manufacturers' libraries.
Prof Epifanio Da Franca
INSTITUTO SUPERIOR TECNICO
Av. Rovisco Pais
P - 1084 LISBOA CODEX
tel: +351/ 1-800637
fax: +351/ 1-899242
INSTITUTO SUPERIOR TECNICO - P - C
AMS - A - P
UNIVERSIDAD DE SEVILLA - AICIA - E - P
UNIVERSITA DI PAVIA - I - P
ITALTEL SIT - I - P
EMPRESA DE INVESTIGACAO E
DESENVOLVIMENTO DE ELECTRONICA - P - P
AD 2000 - 5056, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook