ASIC 0.5 micron CMOS


ACCES - 5048

Keywords 0.7 micron CMOS


Start Date: 01-FEB-90 / Duration: 24 months

[ contact / participants ]


Objectives and Approach

The ACCES project provided European systems and IT users with a multiple-sourced, sub-micron CMOS process offering high packing densities and high speeds. The processes produced are state-of-the-art CMOS ASIC technologies at 0.7 micron dimensions.

The project aimed to develop Europe's capability in advanced ASIC CMOS processes. Sub-micron CMOS technologies were to be developed, demonstrated and qualified at the 0.7 micron (after 2 years) and 0.5 micron (after 4 years) levels. The reduction in dimensions was to be optimised to achieve very high packing density as well as very high speed for digital custom chips. Packing density targets were about 5000 logic gates/mm{2} in 0.7 micron CMOS and over 7000 in 0.5 micron CMOS.

The partners in the consortium are proposing common design rules to their potential customers, resulting in a unique multi-sourcing capability. This approach is further enhanced by the specialisation of the partners in various production levels (from short cycle time prototyping through to high volume deliveries) and application areas (industrial, telecommunications, military, etc).

Progress and Results

Following a demonstration at research scale of the 0.7 micron CMOS process, the process flow was installed in the various industrial sites.

The effort dedicated to the development of advanced CMOS processes overlapped with the work of the Joint Logic Project (JLP, 5080), incorporating the same partners, and after the initial two years of development the project was incorporated into the JESSI Joint Logic Project (7363).

The technology status at that point was as follows. The 1 micron CMOS was considered to have been in volume production since about mid-1991; and 0.7 micron CMOS has been available for initial demonstrators since the third quarter of 1991 at most company sites, and will be released for volume production in the latter half of 1992, when libraries will be available on the open market. The optimisation of the 0.7 micron development is on-going and will be further developed in project 7363. A prototyping status was achieved by all partners for every technology involved in the planned 0.7 micron process supporting the common design rules. These were demonstrated and are now available for exploitation. Commonality has been employed in the design rules, which should enable easy second-sourcing of the technology.

Several demonstrators were designed by the users in the consortium, including:

These are processed in project 7363, LOGIC and have shown functionality.

Due to the work and the involvement of the research centres, the project has also delivered very advanced results for further incorporation in the 0.5 micron technology. Some of the process alternatives developed will be further pursued in project 7363.

The cooperation within the project has enabled the partners to significantly reduce the time needed to develop their CMOS processes, to enhance the quality and depth of knowledge of this development, and to lower the risks involved.


CONTACT POINT

Dr Eric Demoulin
EUROPEAN SILICON
STRUCTURES SA (ES2 SA)
Zone Industrielle
F - 13106 ROUSSET
tel: + 33/ 42-334000
fax: + 33/ 42-334001
telex: 403147 ESS F

Participants

EUROPEAN SILICON
STRUCTURES SA (ES2 SA) - F - C
CNET - F - P
IMEC VZW - B - P
MIETEC NV - B - P
GEC-PLESSEY SEMICONDUCTORS LTD - UK - P
MATRA-MHS - F - P
BRITISH TELECOMMUNICATIONS PLC - UK - A
STANDARD ELEKTRIK LORENZ AG - D - A
TELEFONICA INVESTIGACION
Y DESARROLLO - E - A


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ACCES - 5048, December 1993


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html version of synopsis by Nick Cook