Performance and Reliability of Plastic-Encapsulated CMOS ASICs


PLASIC - 5033

Keywords CMOS-ASIC packaging, plastic packaging


Start Date: 01-JAN-90 / Duration: 39 months

[ contact / participants ]


Objectives and Approach

The PLASIC project was concerned with the performance and reliability of plastic-encapsulated CMOS ASICs, and its goal was to develop guidelines on how to build and evaluate reliable plastic packages for VLSI devices for high reliability applications, such as those encountered in telecommunications, industrial control, and automotive and computer electronics.

Special emphasis was put on the performance and reliability evaluation of complex and advanced plastic-packaged CMOS ASICs, processed using 1.0 micron technologies.

Progress and Results

Stress, moisture penetration, thermal coefficient mismatch and chemical reactions between materials can all influence the performance of VLSI devices. Packaging materials and processes are being studied and optimised, and the stress quantified. The selection of a low stress die attach material and molding compound has been performed, and work on assembly process has been completed. This activity has been demonstrated through the development of a 144 lead plastic quad flat package (PQFP).

An innovative accelerated humidity test method (HAST) has been evaluated and compared to the conventional one (THB). As a result of this study, a method for fast qualification procedures, based on HAST and temperature cycling, has been issued to replace the existing ones, saving qualification time.

Device shifts were investigated and interdependencies between reliability and front-end processing analysed, as well as between reliability and design-rules, in order to optimise the flow of advanced CMOS technologies. All the test structures necessary to analyse the device shifts and parasitic devices are available. Performance evaluation of digital and analogue building blocks has been performed.

A double metal CMOS ASIC with a chip size of 74 mm{2} processed in a 1.0 micron mixed analogue/digital CMOS technology and assembled according to the optimised materials and processes defined. It has been evaluated in terms of performance and reliability. This activity has led to the definition of a qualification procedure for complex high pin-count plastic quad flat packages.

Modelling tools have been developed for the evaluation of the thermo-mechanical stress induced on the ASIC device by the plastic packaging technology.

Two-dimensional plain strain finite element models of PQFP have been developed, resulting in a better understanding of how stresses develop and are transferred to the die during post mold curing. Extensive work has been carried out on these models to study the influence of complete and partial delamination on the thermo-mechanical stress distribution within the package.

3-D finite element techniques with temperature-dependent material properties have been used to investigate the packaging stress on the surface of a die encapsulated in a plastic material.


CONTACT POINT

Dr Gust Schols
MIETEC NV
Westerring 15
B - 9700 OUDENAARDE
tel: + 32/ 55-332211
fax: + 32/ 55-318112
telex: 85739 MIETEC B

Participants

MIETEC NV - B - C
ALCATEL SEL AG - D - P
SGS-THOMSON MICROELECTRONICS SA - F - P
ELEKTRONIK CENTRALEN - DK - A
SGS-THOMSON MICROELECTRONICS SRL - I - A
NATIONAL MICROELECTRONICS
RESEARCH CENTRE - IRL - A


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PLASIC - 5033, December 1993


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html version of synopsis by Nick Cook