Keywords SOI, SIMOX, 0.7 micron
Start Date: 01-MAR-90 / Duration: 24 months
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The SUBSOITEC project aimed to develop high-performance SOI (Silicon On Insulator)/CMOS technologies for future VLSI circuits, which, while competitive with standard bulk CMOS processes, are compatible with them and offer the inherent advantages of SOI technologies.
CMOS circuits with deep sub-micron geometries require very complex and expensive processes on bulk silicon. An acceptable challenger to bulk Si is SOI material which allows, in principle, a significant reduction of the number of process steps leading to an enhancement of the yield of complex VLSI chips and a reduction in cost. Two other advantages of CMOS on SOI are the reduction of parasitic capacitance (which increases circuit speed), and immunity towards radiation and heavy ion effects (needed for space applications), making this technology competitive with bulk BICMOS technology.
The project evaluated a complete SOI/CMOS process with 0.7 micron design rules. The programme included development work on SIMOX (silicon implanted oxide) SOI substrates, on the 0.7 micron SOI technology, on device and physics modelling, on design, and on the test and characterisation of complex VLSI demonstrators. The results allowed a direct economic and performance comparison between bulk and SOI processes.
The work performed in the area of materials fabrication and device evaluation yielded excellent results that compare favourably to work done outside this project. The SOI substrates are among the best available world-wide, even for substrates with very thin top silicon thicknesses. A start-up company SOITEC was generated during the course of the project in order to exploite the results.
The compatibility of SOI processes with standard bulk CMOS technology was considered as a major goal. The portability of bulk design to SOI was studied and implemented. The main difficulties (such as ESD protection devices and the absence of substrate contacts) are now solved. Bulk CMOS design can be easily transported into SOI design. Depending on the nature of the design (digital) no timing issues involved this may require very little effort or a significant effort in case of eg a new SRAM cell, substrate contacts, or asynchronous timing are involved.
Following the end of the project, the ability to realise complex VLSI circuits on SOI with 0.7 micron design rules was demonstrated, and evaluation of the industrial aspect was achieved in a comparison of a design in a CMOS SOI with a CMOS bulk process with the same design rules, and by several SOI demonstrators including a 64 K SRAM and two custom chips. It was also made clear that, only fully depleted devices will deliver the advantages in SOI, as required to compete to the bulk CMOS processing which is expected to become significant at 0.18 µm or below.
The demonstrators have been fabricated at the industrial site. The research partner, LETI, has reported a 30% increase in speed, compared to bulk CMOS, for the same power consumption. This is in accordance with the best results already reported in the literature. During the course of the programme, several papers have been presented and accepted at specialist conferences on SOI technology, demonstrating the high quality of the work.
The 0.7 micron SOI technology is available at one of the industrial sites for further use by external customers, and a start-up company, SOITEC, is manufacturing and bringing the SOI substrate material to market.
Mr Francois Baratte
THOMSON COMPOSANTS MILITAIRES
Rue J-P Timbaud 50
F - 92402 COURBEVOIE CEDEX
tel: + 33/ 1-49053541
fax: + 33/ 1-49053902
telex: 616780 F TMS-CBV
THOMSON COMPOSANTS MILITAIRES
ET SPACIAUX - F - C
FRAUNHOFER GESELLSCHAFT - D - P
CEA - F - P
RESEARCH CENTRE - IRL - P
MARCONI ELECTRONIC DEVICES LTD - UK - P
UNIVERSITY OF SHEFFIELD - UK - P
LEPES-CNRS-GRENOBLE - F - A
SGS-THOMSON MICROELECTRONICS SA - F - A
TELEFUNKEN SYSTEMTECHNIK GMBH - D - A
SEXTANT AVIONIQUE - F - A
SUBSOITEC - 5029, December 1993
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html version of synopsis by Nick Cook