Keywords ESD protection, submicron CMOS technologies, SOI
Start Date: 15-DEC-89 / Duration: 36 months
[ contact / participants ]
Submicron CMOS technologies show increased sensitivity to electrostatic discharge (ESD) due to reduced gate oxide thickness, shallow junctions, lightly doped drain and lack of high resistive interconnections, which tend to reduce circuit reliability. On the other hand, the need for high pin counts, high signal frequencies and advanced analogue performance puts even higher demands on reliability. As a consequence, a special tailor-made protection strategy preventing the inner logic from being damaged by ESD voltages and currents must be found for each application so as to reconcile these opposing trends. Because of the complexity of the problem, reliable guidelines for the optimised design of future protection systems are needed, but are not yet available.
The aim of this project was to significantly increase the ESD hardness of CMOS technologies in the submicron range by improving the understanding of ESD phenomena and developing technology-independent guidelines based on a detailed investigation of relevant parameters and realistic stress models.
Several types of ESD testers and stress models (human body - HBM, charged device and machine models - MM), used to determine the ESD hardness of integrated circuits, were characterised and shown to give non-conformant results, even within the limits of the existing MIL standards. The results are further correlated with field returns. A proposal for the standardisation of ESD stress models and related procedures, in particular for CDM testing is being set up and is under discussion in the standardisation group for ESD testing.
Several new types of ESD testers related to charged device model testing were compared with the prototype built in this project and amongst each other. Reasons for non-conformity were defined.
Failure criteria characterising the effectiveness of ESD protection measures with respect to fatal and latent damage were defined. Besides bulk CMOS, particular attention was paid to problems specific to Silicon-On-Insulator (SOI) technologies, where energy dissipation is considerably hampered by the isolated structure, and conventional protection circuits cannot be used adequately; a new protection device was proposed. Layout variations of devices, different types of devices, protection circuits with varied device combinations and protected circuits were investigated with respect to the different failure criteria for both technologies. Adequate monitor circuits have been developed. A set of guidelines for improving the ESD hardness for processes and circuits was generated and is available for organisations outside the consortium.
A initial set of complex electro-thermal simulation tools, capable of handling the ESD-relevant voltage and current ranges as well as time and frequency domains, was developed. These tools will provide the basis for designing tailor-made protection solutions for future generations of ICs.
The results of the project, in the form of guidelines for the protection of submicron technologies circuitry against ESD, are being transferred to consortia of other ESPRIT projects and are also available to organisations outside the consortium. Recommendations are also being provided to ESD test equipment manufacturers and to the relevant standardisation bodies.
Mr X. Guggenmos
INFORMATIONSSYSTEME AG (SNI)
D - 8000 MÜNCHEN 80
tel: + 49/ 89-41444964
fax: + 49/ 89-41448159
INFORMATIONSSYSTEME AG (SNI) - D - C
IMEC VZW - B - P
NEDERLANDSE PHILIPS BEDRIJVEN BV - NL - P
TECHNISCHE UNIVERSITÄT MÜNCHEN - D - A
Project 5005, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook