Research into Boundary Scan Test Implementation


Project 2478

Keywords boundary scan test, fault diagnosis, design libraries, JTAG


Start Date: 01-JAN-89 / Duration: 36 months

[ contact / participants ]


Objectives and Approach

The aim of this project was to provide the basic knowledge and tools required to implement the boundary scan test (BST) technique and to incorporate it into IC and PCB design and testing. The use of BST will considerably reduce product development costs by improving test generation efficiency and accuracy and eliminating time-consuming and redundant steps in the development of a product.

The project's work was based on IEEE Standard 1149.1-1990 on boundary scan test developed by the Joint Test Action Group (JTAG) and the P1149.1 Working Group.

Progress and Results

The following results were achieved:


CONTACT POINT

Mr Rene Segers
NEDERLANDSE PHILIPS BEDRIJVEN BV
Philips Research Laboratories (Way 3.41)
PO Box 80 000
NL - 5600 JA EINDHOVEN
tel: + 31/ 40-744-928
fax: + 31/ 40-744-924
telex: 35000 PHTC NL

Participants

NEDERLANDSE PHILIPS BEDRIJVEN BV - NL - C
ELEKTRONIK CENTRALEN - DK - P
SGS-THOMSON MICROELECTRONICS SA - F - P
SILICON & SOFTWARE SYSTEMS - IRL - P
THOMSON-CSF/SINTRA-ASM - F - P
THOMSON-CSF - F - P
SIEMENS AG - D - P
INESC - P - A
MATRA SA - F - A


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Project 2478, December 1993


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html version of synopsis by Nick Cook