Keywords boundary scan test, fault diagnosis, design libraries, JTAG
Start Date: 01-JAN-89 / Duration: 36 months
[ contact / participants ]
Objectives and Approach
The aim of this project was to provide the basic knowledge and tools required to implement the boundary scan test (BST) technique and to incorporate it into IC and PCB design and testing. The use of BST will considerably reduce product development costs by improving test generation efficiency and accuracy and eliminating time-consuming and redundant steps in the development of a product.
The project's work was based on IEEE Standard 1149.1-1990 on boundary scan test developed by the Joint Test Action Group (JTAG) and the P1149.1 Working Group.
Progress and Results
The following results were achieved:
- The boundary scan model and description language format developed within the project has been adopted and ratified by the EDIF standards committee for their test extension.
- In the last year of the project, Philips developed, demonstrated and launched onto the world market a comprehensive range of BST testers, ranging from portable field test and diagnosis pods connected to laptop computers, add-on units for logic analysers, through to full-scale production test machines. At the low end, in conjunction with a notebook computer, the product will form the basis of a complete diagnostic field kit for all equipments and system boards equipped with boundary scan. At the high end, and in particular for printed circuit board production environments, the low cost "vector blaster" model is likely to take the test market by storm. The products encapsulate about 70% of the results of the project partners.
- The project partners (notably Siemens) have developed and demonstrated an embryonic board-level test controller chip, SISCO. Future versions could well be employed, one per board, in complex printed circuit boards produced in the late 1990s.
- A static random access memory (SRAM) bank tester chip developed in the project will be marketed by SGS-Thomson. The device enables the autonomous testing of large numbers of SRAM devices on system boards through the BST command loop.
- SGS-Thomson plan to market the TIGAS chip developed within the project to enable the testing of complex and normally difficult-to-test logic "clusters" for BST-equipped system boards.
- SGS-Thomson will market the BST-cell library extensions, which incorporate all the elements needed to implement BST on ASICs. This library will also become part of the IDPS (project 5075) library and therefore be widely available in Europe: it is currently planned for use in the OMI hardware implementations.
- The boundary scan circuits description and data model format, EBST, which is now incorporated into the international electronic data interchange format (EDIF), is available to all the project partners for exploitation. This work is fully compatible with the IEEE 1149.1 standard, and it is therefore likely that one or more of the partners (Silicon & Software Systems, Philips, Electronik Centralen) will market the EBST software toolkit in support of their other project results. Additionally, the EBST results are being integrated into many of the other results from the project.
- GATSBY is a boundary-scan test-pattern generation software package that will be marketed by Silicon & Software Systems as a stand-alone package, as well as by Philips as part of their software support of production test machines.
- The partners have produced a set of boundary scan test silicon compiler module-generators compatible with the popular Genesil and GDT compile products of MentorGraphics (US). These generators will be exploited in the market by Silicon & Software Systems and Matra.
- Elektronik Centralen has ready for exploitation the BSX1 very low cost medium/low speed PC compatible plug-in card (IEEE 1149.1 compatible), which converts an ordinary PC into a bench-top BST tester.
- The final project demonstrator, BSX2, provides an ideal vehicle for the education of engineers in boundary-scan techniques. The partners are considering how best to exploit or disseminate this result.
Mr Rene Segers
NEDERLANDSE PHILIPS BEDRIJVEN BV
Philips Research Laboratories (Way 3.41)
PO Box 80 000
NL - 5600 JA EINDHOVEN
tel: + 31/ 40-744-928
fax: + 31/ 40-744-924
telex: 35000 PHTC NL
NEDERLANDSE PHILIPS BEDRIJVEN BV - NL - C
ELEKTRONIK CENTRALEN - DK - P
SGS-THOMSON MICROELECTRONICS SA - F - P
SILICON & SOFTWARE SYSTEMS - IRL - P
THOMSON-CSF/SINTRA-ASM - F - P
THOMSON-CSF - F - P
SIEMENS AG - D - P
INESC - P - A
MATRA SA - F - A
Project 2478, December 1993
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html version of synopsis by Nick Cook