Keywords DSP, silicon compilation, image processing
Start Date: 01-DEC-88 / Duration: 60 months
[ contact / participants ]
The goal of this project was to develop a design technology environment for the interactive synthesis of complex integrated systems as required for the realisation of real-time information processing subsystems, such as image and graphics processing, post-ISDN home and business peripherals, HDTV, radar, coprocessors, data compression, etc. This would allow system designers to explore different implementation alternatives in terms of several cost criteria (such as chip area, throughput and power dissipation) in a more efficient way. At the same time, the total design time and design effort would be reduced by an order of magnitude.
The behavioural system specifications were described in a mixed functional/procedural language (e.g. VHDL, SILAGE). The synthesis system compiles the specifications in a chip layout using a mixture of knowledge-based and algorithmic techniques. It is oriented towards a set of generic high throughput target architectures with a variable degree of microcode programmability and parallelism. The underlying formalised knowledge base is extracted from the design of industrial demonstrator chips.
Interactivity was based on a pragma concept. Without changing the behavioural specification at the top level, the designer can give structural "hints" to the compilers at different hierarchical design levels. This allows the designer to explore trade-offs in terms of quality factors, such as power and area, for a required throughput as a function of the architectural choice. It also determines hardware, firmware and software trade-offs. In addition, CAD software for both on- and off-chip interprocessor communication was developed.
During the first year the project completed an exhaustive definition phase. Intensive joint workshops resulted in the investigation and definition of different architectural styles that match optimally the requirements of the participants and with sufficient commonality so that collaboration among participants is maximised. A close relationship was set up with the partners of the Basic Research actions ASCIS (3281) and NANA (3280) in order to transfer the knowledge on architecture modelling from these projects to the SPRITE consortium.
In order to fully exploit the system specification through the optimised mapping of the specification onto the different target architectures, a new internal representation language/datastructure, SIL (SPRITE Input Language), was developed. Based on knowledge obtained from the internal representation format developed in the project 97 and the results of the Basic Research Projects ASCIS (3281) and CHEOPS (3215), it was constructed in such a way that it is able to support specification in various languages such as VHDL, SILAGE, ELLA and Hardware C. SIL has been released in the public domain to facilitate the setting of standards in the field of high-level synthesis. SIL is already used in the commercial VHDL-SYN tool (VHDL synthesis) which was released by Philips ED&T at the end of 1993.
In addition, the SPRITE consortium plays a key decision-making role in the SILAGE standardisation committee that has been set up in order to standardise SILAGE as a system specification language for DSP systems.
Work on defining different generic architectural styles resulted in the development of synthesis tools and prototype compilers that have been released to the partners for evaluation in key application areas such as video, telecommunications, image processing, office automation and automotive electronics.
The CATHEDRAL-2nd compiler is an architecture compiler for embedded processor systems. The compiler supports a highly multiplexed architectural style with programmable operators under microcode control. The architectural model of CATHEDRAL-2nd has been extended in order to combine flexible programmable DSP-cores with customised datapaths, memories and logic. This compiler will be retargetable for different core-processors, ranging from in-house developed processor cores towards commercially available cores.
The CBC-compiler is a retargetable central bus compiler for generating microcode for modular architectures, consisting of multiple predefined processor kernels. Interprocessor communication is done via a central bus using a fixed communication protocol. Typical applications for this compiler include speech coding and transmitting techniques like ADPCM, Codec applications, ISDN data transmission and mobile applications (DECT, GSM).
PHIDEO is a compiler targeted at video applications in the consumer industry like standard TV receivers with digitised processing, MAC receivers, IDTV, EDTV and HDTV receivers, digital processing in analogue and/or digital, optical and/or magnetic video registration sets, electronic still picture cameras, and so on. The underlying architectural model consists of datapaths running in parallel at different frequencies if necessary, each having an independent local controller, and distributed memories connected to the datapaths via customised routing network.
CATHEDRAL-2/3 is a compiler for hardwired lowly multiplexed bit-sliced datapaths, which is targeted towards real-time signal processing with a substantial amount of dataflow operations, as-well as data-dependent conditions with upper bounds, as abundant in image processing, front-end audio and telecom processing. Typical applications include for example feature extractors, image coding, equalisers and error correctors. These applications exhibit a high data rate and operate on multi-dimensional data, involving a combination of complex arithmetic and control flow (loops and conditions). Training courses on CATHEDRAL-2/3 have been organised successfully for the external world in 1993. The compiler is hooked to Mentor/EDC's commercial DSP Station, in order to ease the transfer to designers.
ASSASSIN is a compiler for asynchronous interface circuits. It synthesises asynchronous control circuits starting from a timed Signal Transition Graph (Specification) and generates a logic description which is race and hazard free. This compiler has been transferred to the OMI-EXACT project (6143).
The RETLAB-tool, which has been developed in the context of the PHIDEO compiler has been transferred to Philips ED&T. It is a datapath compiler using the retiming techniques for optimisation, complementing existing logic synthesis tools. It is commercialised under the name Optima as a stand-alone tool and as a part of Locam, Philips ED&T's logic synthesis product line.
The CATHEDRAL technology is currently being transferred to EDC, a Belgian SME with shareholders Mentor Graphics, Philips and IMEC. EDC is commercialising the CATHEDRAL compilers as part of their DSP Station design environment.
The Swiss company Landis & Gyr joined the SPRITE consortium via an agreement on early exploitation of results.
Mr Patrick Pype
B - 3001 LEUVEN
tel: + 32/ 16-281207
fax: + 32/ 16-281515
IMEC VZW - B - C
NEDERLANDSE PHILIPS BEDRIJVEN BV - NL - P
RACAL RESEARCH LTD - UK - P (till 11/91)
SIEMENS AG- SEMICONDUCTOR GROUP - D - P
INESC - P - A
DRA (DEFENCE RESEARCH AGENCY) - UK - A
TECHNISCHE UNIVERSITEIT EINDHOVEN - NL - A
UIVERSITEIT TWENTE - NL - A
CGED - UK - A (till 8/92)
SPRITE - 2260, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook