APACHIP - 2075
Keywords TAB, VLSI, packaging
Start Date: 16-JAN-89 / Duration: 48 months
[ contact / participants ]
Objectives and Approach
The APACHIP project addressed the field of advanced VLSI packaging. It was aimed at providing advanced packaging solutions for multichip modules and for single chip package applications. The project developed packaging techniques for highly integrated bipolar circuits requiring liquid cooling, and also for the even more integrated MOS VLSIs, where air-cooling techniques can still be applied. VLSI chips, whether bipolar or MOS, are assembled using tape automated bonding (TAB). The necessary TAB tape was developed in the project and introduced to the European market.
The efficient interconnection of VLSI chips requires the availability of high-density high-performance substrates. Two different approaches of high-density substrate realisation were tackled in APACHIP. One proceeds from printed circuit board-like technology to achieve very dense interconnection and miniature laser-formed vias; the other approach uses thin film deposited and electrolytically reinforced copper lines separated by polyimide layers. This copper-polyimide structure is applied on a large ceramic substrate, also developed in the project. A new connector concept was defined to test the multichip or single chip substrates populated with TAB chips and to connect them into systems. Electrical modelling, reliability aspects and new inspection methods were also included in the project.
Progress and Results
The following results were achieved:
- TAB tapes with 316 input/output leads at a pitch of 125 micron on 70 mm tape; MCTS can supply this in industrial quantities.
- Bull has developed bonding equipment and processes that include lead-forming and bonding of both inner and outer leads at 125 micron pitch, with 12 mm ICs on 70 mm tape, onto multi-chip substrates. Developments are in progress on bumpless TAB and on very fine pitch wire bonding (down to 100 micron). Bull has also established the different process steps for a multilayer polyimide-copper substrate technology as the basis for multi-chip modules with up to five metal layers on a 10 cm square co-fired ceramic substrate (100 micron pitch of tracks and via holes).
- Hoechst CeramTec has demonstrated improved fabrication technology and realised a number of new packages, notably a single-chip package with multilayer metallisation and improved heat transfer (using a tungsten-copper insert), a pin grid array with inner lead pitch of 200 micron, and a 10 cm square multi-chip package substrate containing 888 corrector pads.
- Souriau has designed the high-density, high-frequency connectors and has provided production-quality prototypes, used in demonstrator modules by Bull/Hoechst CeramTec and GEC-Marconi. Pre-industrial tooling has been fabricated. An application with a Siemens-Nixdorf substrate is being designed.
- High-density organic multi-chip substrates (Siemens-Nixdorf and GEC Marconi) have achieved world-class specifications in terms of low resistance conductor tracks at pitches down to 80 micron, via holes as small as 30 micron in diameter, controlled impedance tracks, and up to 17 metal layers (signal and power/ground). The aim is to exploit these capabilities for professional and consumer products, selecting the electronic devices (eg CMOS, ECL), and the appropriate interconnection, packaging and cooling techniques for the different types of multi-chip module required. Siemens-Nixdorf is already planning to use such substrates for its next generation computers.
- Scanning acoustic microscopy has been successfully applied by NMRC to investigating advanced packaging structures, including voids and delaminations in large area die-attach and co-fired ceramic substrates and voids in hermetic package seals.
- Extensive thermal modeling at GEC-Marconi, Siemens Nixdorf and Bull has led to the successful development of several water-cooled and fluorocarbon immersion-cooled demonstrators. Dedicated test chips have been developed by NMRC and used for the thermal management R&D. The multi-chip modules of GEC-Marconi, Siemens Nixdorf and Bull/Hoechst CeramTec, described above, have been evaluated for thermal and mechanical characteristics.
- Electrical modelling for the high density interconnections in the substrates (Technische Universität Berlin) and the connectors (Souriau) enables the prediction of characteristic impedance and crosstalk, thus reducing the cost and timescale of the design stage.
The marketable products generated by the project include packaged electronic sub-assemblies of electronic systems and also packaging material supplies (TAB tapes, ceramic packages, etc) necessary for an advanced European electronic industry.
Mr Karel Kurzweil
Rue Jean Jaures
F - 78340 LES CLAYES-SOUS-BOIS
tel: + 33/ 1-30807000
fax: + 33/ 1-34627879
telex: 696054 BULLSA F
BULL SA - F - C
HOECHST CERAMTEC AG - D - P
RESEARCH CENTRE - IRL - P
SOURIAU & CIE - F - P
TECHNISCHE UNIVERSITÄT BERLIN - D - P
INFORMATIONSSYSTEME AG (SNI) - D - P
MCTS - F - P
GEC RESEARCH LABORATORIES - UK - P
APACHIP - 2075, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook