Keywords non-volatile memories, oxynitrides, multifunction CMOS technologies, cell libraries, ASIC applications
Start Date: 15-DEC-88 / Duration: 60 months
[ contact / participants ]
The goal of this project was the integration of new-generation reprogrammable, read-only memory devices (both EPROM and EEPROM) for the application-specific IC (ASIC) market into:
At the start of the project the availability of cell libraries and CAD tools for non-volatile memory was quite limited. One of the main objectives of the project has thus been the development of cell libraries for EPROM and EEPROM blocks and distributed memory, together with all the support circuitry, such as decoders, sense amplifiers, high voltage generators, etc. CAD tools to design and correctly match memory blocks of arbitrary size had also to be developed, as well as routing tools to handle the special high voltage requirements.
Several batches have been processed by Plessey, SGS-Thomson and characterised, with the collaboration of IMEC and NMRC, in order to evaluate the effect of cell size reduction, layout and processing options on cell performance. Valuable simulation work has also been carried out. Concerning the processing, particular attention has been given to the impact on the cells of the implementation of both EPROM and EEPROM in the basic CMOS process. As for the cell architecture, several innovative cells have been studied at IMEC. The most promising ones include the split-gate cell with enhanced injection, and the trench gate oxide cell.
The work on CAD tools and cell library has included the generation of a power distribution checker, the investigation of automatic layout tools for electrically reconfigurable logic arrays, and the development of EPROM and EEPROM generators allowing the maximum modularity in terms of number of bits and number of words. A methodology for testability and a Quality Assurance Test program have also been developed.
The successful execution of the project is to be proven by product-oriented demonstrators, containing everything from small distributed memory registers to large embedded memory blocks. Following the workshop on "Non-volatile functions incorporated into ASICs: new opportunities for small and medium enterprises" held during the 1989 ESPRIT Conference, several SMEs have become associated with the IC manufacturers in the project, to design circuits addressing innovative new applications. The demonstrators which have been developed include:
As a result of the first phase of the project, two technologies (incorporating EPROM and EEPROM, respectively) have been transferred by ST to production to make micro controllers with embedded memory for applications including credit cards, pay-TV, computer peripherals, and in the growing automotive market.
The EEPROM technology, at 1.4 micron, developed by GEC-Plessey is now being used for products. A shrink path to a 1µm version of the process has been demonstrated and the implications of adding the necessary process steps to the sub-micron (0.7 micron and 0.5 micron) CMOS processes have been evaluated.
In the last year of the project (as project 7802), ST and MHS (which replaced Eurosil) concentrated on non-volatile technology at 0.8 micron based on flash EEPROM (ST) and on double-poly floating gate cells (MHS). ST, GEC-Plessey and MHS also supported the development of new demonstrators by GEMPLUS, INESC, MIKRON and Fraunhofer Institute.
Dr G. Iannuzzi
Via Olivetti 2
I - Agrate Brianza
tel: + 39/ 39-6035-028
fax: + 39/ 39-6035-820
telex: 330131 SGSAGR
GEC-PLESSEY SEMICONDUCTORS - UK - C
SGS-THOMSON MICROELECTRONICS SRL - I - P
SGS-THOMSON MICROELECTRONICS SA - F - P
EUROSIL ELECTRONIC GMBH - D - P
MHS - F - A
DEISTER ELECTRONIC GMBH - D - A
FRAUNHOFER - D - A
IMEC VZW - B - A
UNIVERSITA DI BOLOGNA - I - A
UNIVERSITY COLLEGE CORK - IRL - A
MIKRON GMBH - D - A
GEMPLUS CARD INTERNATIONAL - F - A
IRIS - I - A
INESC - P - A
INPG - GRENOBLE - F - A
APBB - 2039 + 7802, December 1993
please address enquiries to the ESPRIT Information Desk
html version of synopsis by Nick Cook